1. Field of Invention
The present invention relates to a memory, and more specifically, to a memory apparatus and a method thereof for operating a memory.
2. Description of Related Art
A memory is a semiconductor device designed for storing information or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequentially, the demand for high storage capacity memories is getting more.
Among various types of memory products, a non-volatile memory allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power to the memory is terminated. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Conventional flash memory cells store charge on a floating gate. The stored charge changes the threshold voltage Vt of the memory cell. In a READ operation, a read voltage is applied to the gate of the memory cell, and whether or not the memory cell turns on (e.g. conducts current) indicates the programming state of the memory cell. For example, memory cell that conducts current during a READ operation might be assigned a digital value of “1”, and a memory cell that does not conduct current during a READ operation might be assigned a digital value of “0”. Charge is added to and removed from the floating gate to program and erase the memory cell, i.e., to change the stored value from “1” to “0” or from “0” to “1”.
Another type of memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, rather than the conductive gate material used in floating gate devices. When a charge-trapping cell is programmed, the charge is trapped and does not move through the non-conductive layer. The charge is retained by the charge trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. Charge-trapping cells can be operated as two-sided cells. That is, because the charge does not move through the non-conductive charge trapping layer, charge can be localized on different charge-trapping sites.
With the amount of the memory cells grows higher, the threshold voltage distribution range of the memory cells therefore becomes very large. FIG. 1 and FIG. 2 are examples of threshold voltage distribution diagrams of a conventional 1-Megabite memory and a conventional 1-Gigabite memory respectively. Both of the memories have a plurality memory cells, each of which are capable of storing two bits of data. The horizontal axis represents the threshold voltage of a memory cell, and the vertical axis represents the amount of memory cells. The threshold voltage distribution of the 1-Megabyte memory includes distribution regions 21 to 24. SW1 is the sensing window between the high boundary of distribution region 21 and low boundary of distribution region 22. Similarly, SW2 is the sensing window between distribution regions 22 and 23. SW3 is the sensing window between distribution regions 23 and 24. Distribution regions 25 to 28 are threshold voltage distribution regions of the 1-Gigabyte memory. Sensing windows SW4 to SW6 are the sensing windows of the 1-Gigabyte memory. As shown in FIGS. 1-2, the ranges of distribution regions 25 to 28 are generally larger than the ranges of distribution regions 21 to 24, which causes sensing windows SW4 to SW6 of the 1-Gigabyte memory are much narrower than the sensing windows SW1 to SW3 of the 1-Megabyte memory. Thus, when the capacity of a memory grows higher, the diversity of the threshold voltages of the memory cells of the memory becomes larger, and the sensing windows of the memory become narrower, which causes difficulty to perform the sensing process for distinguishing states of memory cells of the memory when reading the memory.